The present invention pertains to converting from an analog video signal to a digital video signal, and in particular to automatically adjusting phase and frequency of a clock for converting from an analog signal to a digital signal, and particularly for .
Presentations using multimedia projection display systems have become popular for purposes such as sales demonstrations, business meetings, and classroom sessions. In a common mode of operation, multimedia projection display systems receive analog video signals from a personal computer (PC). The video signals represent still, partial-, or full-motion display images of the type rendered by the PC. The analog video signals are converted into digital video signals to control a digitally-driven display object, such as a transmissive liquid crystal display (LCD), to form the display images for projection onto a display screen.
Two common types of multimedia projection display systems are LCD projectors and LCD projection panels. An LCD projector includes a transmissive LCD, a light source, and projection optics to form ad and project display images in the manner describes described above. An LCD projection panel includes a similar transmissive LCD to form the display image, but operates with a conventional overhead projector (OHP) having a light source and projection optics, to project the display image onto a display screen. Examples of such LCD projectors and LCD projection panels are sold under the respective trademarks LITEPRO and PANELBOOK by In Focus Systems, Inc. of Wilsonville, Ore., the assignee of the present application.
One desirable feature for multimedia display systems is compatibility with the various analog video signal modes generated by various PC""s. These modes generally range from 640xc3x97480 to 1600xc3x971200 resolutions provided at image refresh rates of 60 to 100 Hz. The resolution expresses the number of horizontal and vertical pixel elements that can be turned on and off. Given the variety of resolution modes, multimedia display systems include an interface that converts analog video signals of various modes to digital video signals capable of controlling the LCD.
In general, analog video signals comprise an analog image data signal for each of the primary colors red, green and blue, and digital timing signals, which may include a pulsed horizontal synchronizing signal (Hsync) and a pulsed vertical synchronizing signal (Vsync), or a composite sync signal. The individual analog color signals are generated from bit data in a memory portion of the PC, using three digital-to-analog (D/A) converters, one for each of red, green and blue. FIG. 1a shows an exemplary analog signal waveform 1, with plateau regions (pixel data components) 2 that correspond to the color level of individual pixels of the image display. Consecutive pixel data components 2 are connected by signal transition regions 3. The digital timing signal controls the raster-scanning of the analog video data signals across the monitor screen. The Hsync pulse controls the horizontal raster scan rate, and the Vsync pulse controls the image (or frame) refresh rate. In the case of a composite sync signal, a conventional sync separator is first used to obtain the horizontal and refresh signals.
As shown in FIG. 1d, each video frame 9 is usually produced to have a central active video region 11 surrounded by an inactive (xe2x80x9cblankedxe2x80x9d) margin 13. The resolution refers to only the pixels in the active video region.
Because the LCD used in multimedia display systems require requires digital video signals, either the LCD or the system normally has an analog to digital (A/D) signal converter for converting the PC-generated analog video signals into a digital format suitable for driving the LCD. The A/D signal converter is usually combined with a phase-locked loop (PLL), which may comprise a phase comparator, a low-pass loop filter, and a voltage-controlled oscillator (VCO) formed in a loop to generate a feedback signal that locks into Hsync. In order to generate a selected multiple n of clock pulses for each period of Hsync, a divide-by-n counter is added to the feedback loop between the VCO output and the phase comparator.
An example of a pixel clock waveform 4 is shown in FIG. 1a. The number n of individual pixel pulses per Hsync pulse may be set by reference to the resolution mode of the analog video source. To set the resolution mode, certain characteristics of the analog video signal, such as Hsync and Vsync, may be used to refer to a mode look-up table stored in the display system CPU. The number n should be set to equal the number of pixel data components in each horizontal line of the scanned analog signal, including those active video data region 11 and the blanked margin regions 13 (see FIG. 1d) on either side of the active region. For example, for a screen resolution of 640xc3x97480, n may be set at about 800 to include the blanked regions on either side of the 640 pixel-wide active video data region. Thus, the pixel clock would sample the continuous stream of analog image data 800 times along each horizontal line of the frame.
FIG. 1a shows the desired relationship between the analog video data signal 1 and the pixel clock signal 4. The number n of pixel clocks 5 is set to establish a one-to-one relationship between pixel clock pulses 5 and pixel data components 2 of the analog data signal 1. This one-to-one relationship requires that the pixel clock signal frequency be equal to the analog video data signal frequency. Under this relationship, each pixel data component 2 of the analog signal is sampled by a single pixel clock pulse 5, which reads the instantaneous voltage value of the pixel data component so that it can be digitized. Since the pixel clock pulses 5 have xe2x80x9cjitterxe2x80x9d zones 6 at their leading and trailing edges, the clock pulses 5 should be registered with the centers of the pixel data components 2, so that the sampling is not randomly pushed by the jitter into the transition regions 3 of the analog video signal.
The stream of digitized values form forms the digital video data signal, which is addressed to the LCD to appropriately set LCD pixels at blank (black) or selected activated (non-black) status to replicate the image defined by the analog video signal.
Unfortunately, such A/D conversion is often imperfect due to errors in the pixel clock sampling of the analog signal. Such sampling imprecision gives rise to frequency (also know as xe2x80x9ctrackingxe2x80x9d) and xe2x80x9cphasexe2x80x9d errors, both of which may degrade the quality of the LCD image.
Referring to the analog video signal 1 and pixel clock signal 4xe2x80x2 in FIG. 1b, tracking error results from the number n of pixel clocks being improperly set. As discussed above, the number n of pixel clocks should be equal to the number of pixel data components 2 of each horizontal line of analog video data signal. In FIG. 1b, the improper setting of n results in the pixel data components 2 not being sampled at a consistent point. For instance, n is set too large in clock signal 4xe2x80x2 (i.e. the clock signal frequency is too high). The resulting crowding of the pixel clock pulses 5xe2x80x2 yields an additive leftward drift of the pixel clock pulses 5xe2x80x2 relative to the pixel data components 2 of the analog video data signal 1. Such drift causes sampling in the transition regions 3. For instance, as indicated by positional bracket A, the leading edges 7xe2x80x2 of the third through the sixth clock pulses 5xe2x80x2 sample in transition zones 3 of the analog video signal 1. Accordingly, the transition zone data will be erroneous, and the image information from adjacent non-sampled pixel data components 2 will be missing from the digitized video signal. If n is erroneously set large enough, the pixel clock pulses may be so crowed crowded that individual analog pixel data components 2 may be double-sampled. On the other hand, if n is set too small (i.e. the pixel clock signal frequency is too low), the dispersion of the pixel clock pulses results in a rightward drift wherein sampling may also occur in the transition regions. In all of these cases, the erroneous sampling provides erroneous video signal data that may degrade the LCD image quality.
Phase error may occur even if the pixel clock signal frequency equals the analog video data signal frequency. As shown in pixel clock signal 4xe2x80x3 in FIG. 1c, the clock phase may be erroneously set such that every pixel clock pulse samples a transition region 3 of the analog video data signal. Leading edge jitter makes such phase error more likely, since if the jitter zones straddle the intersections 8 of the pixel data components 2 and transition regions 3 of the analog video data signal 1, the voltage will be randomly sampled on either side of the intersection 8. In any case, phase error is undesirable in generating undesirable noise, or xe2x80x9csnowxe2x80x9d in the LCD video image.
In order to eliminate tracking and phase errors in existing projection systems, manual controls are provided on projection systems which permit an operator to adjust the number n of clocks 5 and the phase of the pixel clock waveform. These controls are adjusted until the projected image appears satisfactory to the eye of the system operator. While such manual error control is usually effective in achieving an acceptable image quality, such manual control is time-consuming and inhibits the user-friendliness of the projection system.
Thus, in light of these disadvantages, it is a principle principal object of the present invention to provide an apparatus and a method for producing a digital video signal from a an analog video signal that automatically corrects phase and tracking errors.
It is another object of the present invention to provide such automatic phase and tracking error correction for a wide range of analog video signal resolution modes.
It is another object of the present invention to provide an apparatus and a method for producing a digital video signal from a an analog video signal that automatically corrects the horizontal position of a video image on the display object.
In accordance with a preferred method of the present invention, a digital video signal is produced from an analog video signal which includes an analog video data signal that is operable to be raster scanned in lines across a CRT screen to form consecutive frames of video information, the raster scanning controlled by use of a horizontal synchronizing signal (Hsync) that controls a line scan rate, and a vertical synchronizing signal (Vsync) that controls a frame refresh rate, to produce consecutive frames of video information. The digital video signal is produced by generating a pixel clock signal with pixel clocks for repetitively sampling instantaneous values of the analog video data signal, and digitizing the active image width of the analog video data signal based on the pixel clock sampling. An expected width E, measured in number of pixel clocks, of a video image producible by the analog video signal is estimated, and an actual width W, measured in number of pixel clocks, of the actual video image producible by the analog video signal is calculated. The actual width W is compared with the expected width E. When E does not equal W, at least one of a frequency component and a phase component of the pixel clock signal is adjusted until E equals W.